The invention relates to an output circuit in a semiconductor integrated circuit, and more particularly to an output circuit having current mirror circuits in a semiconductor integrated circuit.
One of the most importance for circuit design of semiconductor integrated circuits is an improvement in high integration of the semiconductor integrated circuits. Indeed, the importance of high integration of the semiconductor integrated circuits is on the increase. As the output circuits are involved in the semiconductor integrated circuits, a minimization of the output circuit and thus a reduction of a occupied area by the output circuit are essential to improve the high integration of the semiconductor integrated circuits.
A typical circuit structure of the conventional output circuit, particularly an output circuit which exhibits a controllable output current will be described with reference to FIG. 1. The conventional output circuit is formed between a high potential side power supply line 1 and a low potential side ground line 3 so as to drive the output circuit by a power which is supplied from a power supply through the high potential side power supply line 1. The output circuit has a signal input terminal 2 which receives input digital signals and an output terminal 4 through which output signals are delivered. The output circuit includes a p-type MOS transistor P1, an n-type MOS transistor N1 and first and second current mirror circuits 5 and 6. The circuit structure of the output circuit may be regarded as a modification of the CMOS circuit structure wherein the p-type and n-type MOS transistors are connected to the output terminal 4 through the first and second current mirror circuits 5 and 6.
Thus, the p-type MOS transistor P1 which serves as a switching device is arranged at a high potential side in the output circuit. More particularly, the p-type MOS transistor P1 is connected at its source side to the high potential side power supply line 1 which supply a power to the output circuit. The p-type MOS transistor P1 is further connected at its drain side to the first current mirror circuit 5. The p-type MOS transistor P1 is further connected at its gate electrode to the signal input terminal 2 which receives digital input signals so as to exhibit a high speed switching operation based upon digital input signals which are transmitted to the gate electrode of the p-type MOS transistor P1 through the signal input terminal 2. When the gate electrode of the p-type MOS transistor P1 receives the high level signal, the p-type MOS transistor P1 takes OFF state. If the gate electrode of the p-type MOS transistor P1 receives the low level signal, the p-type MOS transistor P1 takes ON state.
The n-type MOS transistor N1 which also serves as a switching device is arranged but at a low potential side in the output circuit. The n-type MOS transistor N1 is connected at its source side to the ground line which supply the ground potential to the output circuit. The n-type MOS transistor N1 is further connected at its drain side to the second current mirror circuit 6. The n-type MOS transistor N1 is further connected at its gate electrode to the signal input terminal 2 which receives digital input signals so as to exhibit a high speed switching operation based upon digital input signals which are transmitted to the gate electrode of the n-type MOS transistor N1 through the signal input terminal 2. When the gate electrode of the n-type MOS transistor N1 receives the high level signal, the n-type MOS transistor N1 takes ON state. If the gate electrode of the n-type MOS transistor N1 receives the low level signal, the n-type MOS transistor N1 takes OFF state.
The first current mirror circuit 5 is arranged between the p-type MOS transistor P1 serving as a switching device and the output terminal 4. The first current mirror circuit 5 includes an n-type transistor N51 and p-type transistors P52 and P53. The p-type MOS transistor P53 is arranged on an output stage in the first current mirror circuit 5. The p-type MOS transistor P53 is connected at its source side to the drain side of the p-type MOS switching transistor P1. The p-type MOS transistor P53 is also connected at its drain side to the output terminal 4. The p-type MOS transistor P53 and the p-type MOS transistor P52 are connected to each other through those gate electrodes and source sides respectively. The p-type MOS transistor P52 and the n-type MOS transistor N51 are connected to each other through those drain sides. The p-type MOS transistor P52 has a short circuit connection between its gate and drain sides. The n-type MOS transistor N51 is grounded at its source side. The gate electrode of the n-type MOS transistor N51 receives a constant voltage V.sub.RP. The n-type MOS transistor N51 serves as a current source. The p-type MOS transistor P52 controls a source-drain current of the p-type MOS transistor P53 so that the respective source-drain currents of the p-type MOS transistors P1 and P53 are approximately proportional to each other. The ratio of the respective source-drain currents of the p-type MOS transistors P52 and P53 is defined by the ratio of channel widths thereof.
The second current mirror circuit 6 is arranged between the n-type MOS transistor N1 serving as a switching device and the output terminal 4. The second current mirror circuit 6 includes a p-type transistor P61 and n-type transistors N62 and N63. The n-type MOS transistor N63 is arranged on an output stage in the second current mirror circuit 6. The n-type MOS transistor N63 is connected at its source side to the drain side of the n-type MOS switching transistor N1. The n-type MOS transistor N63 is also connected at its drain side to the output terminal 4. The n-type MOS transistor N63 and the n-type MOS transistor N62 are connected to each other through those gate electrodes and source sides respectively. The n-type MOS transistor N62 and the p-type MOS transistor P61 are connected to each other through those drain sides. The n-type MOS transistor N62 has a short circuit connection between its gate and drain sides. The p-type MOS transistor P61 is connected to a high potential side power supply line which supplies a high voltage V.sub.DD. The gate electrode of the p-type MOS transistor P61 receives a constant voltage V.sub.RN. The p-type MOS transistor P61 serves as a current source. The n-type MOS transistor N62 controls a source-drain current of the n-type MOS transistor N63 so that the respective source-drain currents of the n-type MOS transistors N1 and N63 are approximately proportional to each other. The ratio of the respective source-drain currents of the n-type MOS transistors N62 and N63 is defined by the ratio of channel widths thereof.
Such conventional output circuit is, however, engaged with the following disadvantages. As described above, the p-type MOS transistors P1 and P53 are connected in series on the output stage in the output circuit in the semiconductor integrated circuits. The n-type MOS transistors N1 and N63 are also connected in series on the output stage in the output circuit. It appears that a relatively large source-drain current flows through either the p-type MOS transistors P1 and P53 or the n-type MOS transistors N1 and N63. Namely, it is required that the source-drain currents of the p-type MOS transistor P1 and P53 are the same. Similarly, it is required that the source-drain currents of the n-type MOS transistors N1 and N63 are the same. That is why it is required to so design both the p-type MOS transistors P1 and P53 as to have the same channel size and thus the same channel width and length. Of course, the n-type MOS transistors N1 and N63 are so designed as to have the same channel size.
Further, as described above, the p-type transistor P53 and P52 respectively exhibit source-drain currents which are proportional to each other. Thus, the p-type transistor P53 and P52 respectively are designed as to have channel widths which are proportional to each other. The ratio of the source-drain currents of the p-type MOS transistors P52 and P53 is defined by the ratio of the channel widths thereof. It is required for a high speed driving of a load that either the p-type MOS transistor P53 or n-type MOS transistor N63 on the output stage has an extremely large source-drain current as compared to the source-drain current of the p-type MOS transistor P52. This results in that the channel widths of both the p-type and n-type MOS transistors P53 and N63 are also extremely large as compared to the channel widths of the p-type and n-type MOS transistors P52 and N62. The transistors P53 and N63 on the output stage of the output circuit are forced to have an extremely large size as compared to the transistors P52 and N62 in logic circuits. Physically, the MOS transistors P52 and N62 has a small channel width no more than 10 micrometers to 20 micrometers. In contrast, both the p-type transistors P1 and P53 are required to have extremely large channel widths of approximately 2500 micrometers and large channel lengths of approximately 3 micrometers. The n-type MOS transistors N1 and N63 are also required to have extremely large channel widths of approximately 1250 micrometers and large channel lengths of approximately 3 micrometers. Each of the transistors P1, N1, P53 and P63 on the output stage in the output circuit requires an extremely large occupied area as compared to the other transistors in the logic circuit in the output circuit.
It is therefore necessary to improve a high integration and thus to minimize a occupied area of the output circuit involved in the semiconductor integrated circuits. Scaling down of each of the transistors on the output stage in the output circuit is difficult due to the requirement of those large source-drain current. Thus, a reduction of the number of transistors on the output stage in the output circuit is essential to improve a high integration of the output circuit and thus to minimize the occupied area of the output circuit.
It is, therefore, required to develop a novel output circuit which is so designed as to reduce the number of transistors having an extremely large occupied area arranged on the output circuits.